1. Field
Cache coherency in a multi-processor system.
2. Description of Related Art
In a multi-processor system having multiple caches, each cache may have a copy of a piece of data stored in memory. Problems arise when multiple data copies in the caches are not coherent. Various techniques have been developed to ensure data coherency. For example, when the data in one cache is modified, other copies of the data are marked as invalid so that they will not be used.
A copy of data in the cache is often referred to as a cache line, a memory line, or a line. A snooping operation refers to the process in which an agent of a bus monitors the bus for memory transactions, e.g., a read/write operation to a main memory location which may also reside in a cache. The agent may record the states of the cache lines involved in the memory transactions in a directory, e.g., a snoop filter. The state of the cache line may indicate whether the line has only one valid copy outside of the main memory, has multiple valid copies shared by multiple caches, or has been invalidated. A data entry in the snoop filter is often indexed by its address in the main memory.
It is generally desired to have a large snoop filter that provides coverage many times of the total size of processor caches (e.g., 8× coverage, which is a term of art that indicates the snoop filter can hold information describing about eight times as many cache lines as the caches subject to the snoop filter can hold). A large snoop filter may increase the hit ratio of the processor caches and improve system performance. However, as the size of processor caches increases over time, circuit designers are hard pressed to provide even 1× coverage due to die size limitations. Thus, the snoop filter sometimes may run out of space to record the state of a line for a new memory transaction, and may need to evict an entry from the snoop filter to accommodate the new transaction. One an entry is evicted from the snoop filter, a back-invalidation message is sent to every processor cache that potentially holds a valid copy of the line associated with the evicted entry. Experiments show that a significant number of cache misses (e.g. 20%) are due to back invalidations of a cache line that was about to be used.